This website contains supplementary information on neuron machine (NM) special purpose hardware architecture computing deep belief networks (DBNs). As we hope it will be clear through the source codes presented here, the NM hardware architecture exhibits several orders of magnitude better performance-resource ratio compared to other DBN systems, which implies smaller chip area and power consumption, and better computational speed using the same resource.

Although we implemented the system on an FPGA chip, it is extremely unrealistic for readers to reproduce the system and verify what we proposed in the paper, requiring a FPGA circuit board, VHDL programming, and sophisticated development software. For this reason, we developed a self-contained hardware simulator simulating our hardware systems on MATLAB, and a full source code is provided here. Even though the source code is coded in a sequential language, it is cycle-accurate and simulates various register-transfer-level (RTL) components in the same way as the hardware. Readers can execute the simulator on the fly and verify ideas described in the original paper.

The technical paper supported by this hardware simulator can be found in IEEE IJCNN 2014 conference proceeding with title “Computation of Deep Belief Networks Using Special Purpose Hardware Architecture.”